The present invention relates to a communication system, a reception apparatus and method, a recording medium and a program, and more particularly to a communication system, a reception apparatus and method, a recording medium and a program wherein even where means for synchronizing a reception clock with a transmission clock is not available, data transmitted can be received accurately while a high transmission capacity is assured.
Usually, in data communication, it is necessary for an apparatus on the receiver side of data to keep a reception clock used for definition of a sampling period in synchronism with a transmission clock of the sender side in order to correctly sample the values (1, 0) of data transmitted from an apparatus of the sender side.
Two methods are available for synchronizing the reception clock with the transmission clock. According to one of the methods, the apparatus of the receiver side receives supply of a clock same as the transmission clock from the sender side or an external apparatus and uses the received clock as the reception clock. According to the other method, the apparatus itself of the receiver side reproduces a clock same as the transmission clock and uses the reproduced clock as the reception clock.
According to the former method, a line for sending a clock therethrough is required separately from a line for sending data therethrough. Therefore, the application of the method is restricted only to communication on a board or communication wherein a plurality of wiring lines are available.
FIG. 1 shows a configuration of a communication system which includes a transmission section 1 and a reception section 2.
Referring to FIG. 1, in order to send a clock from the transmission section 1 to the reception section 2 to establish synchronism of a reception clock, it is necessary to prepare a clock line 4 between the transmission section 1 and the reception section 2 separately from a data line or lines 3.
On the other hand, the latter method is used in serial communication (1-channel communication). In order for an apparatus on the receiver side to reproduce a transmission clock, a PLL (Phase Locked Loop) is used popularly.
FIG. 2 shows an example of a configuration of a PLL.
Referring to FIG. 2, the PLL shown includes, for example, a low-pass filter (LPF) 11, a phase comparator 12, a loop filter 13, and a voltage controlled oscillator (VCO) 14. The phase comparator 12 compares the phases of an output of the LPF 11 and an output of the VCO 14 with each other and outputs a phase error. The loop filter 13 compensates for the output of the phase comparator 12 and outputs a resulting signal to the VCO 14. The VCO 14 generates a clock of a phase corresponding to the output of the loop filter 13 and outputs the clock to the phase comparator 12 and the outside of the circuit. The clock outputted from the PLL is used as a reception clock.
For example, where transmitted and received signals are a bi-phase signal, the received signal exhibits a peak at a clock frequency and at another frequency equal to twice the clock frequency. In this instance, the transmission clock can be reproduced also by the receiver side by extracting the clock frequency by means of the LPF 11 and applying the PLL by the configuration at the following stage.
Where the PLL having such a configuration as described above handles a signal particularly of a high frequency region, it must be formed from an analog circuit and is not suitable for high integration. Further, since the PLL in principle requires considerable time before the phase is locked (synchronized), it is not suitable particularly for high speed communication.
Japanese Patent Laid-Open No. 2003-263404 discloses a technique wherein, upon starting of serial communication, a reset signal is transmitted to a reset terminal of the receiver side and the reset signal is used in later communication thereby to implement a circuit for communication of a small circuit scale.
Japanese Patent Laid-Open No. 2002-7322 discloses another technique wherein, where transmission and reception of data are performed between different units which use clocks which are same in frequency but different in phase between the sender side and the receiver side, a variable delay circuit whose delay time is controllable is provided on the unit on the receiver side to achieve stabilized data communication.
As described hereinabove, each of the two methods for assuring synchronism in the apparatus of the receiver side is disadvantageous in that a line for exclusive use for a clock is required in addition to a data line or that high integration cannot be achieved and much time is required to establish synchronism. Nevertheless, if the disadvantage is not permitted, then accurate data cannot be restored while the transmission capacity is assured.
Here, a reception apparatus is considered which fetches data successively transmitted thereto only at fixed intervals without establishing synchronism of a reception clock in order to perform communication without depending upon any of the two methods. The reception apparatus does not include synchronizing means by a PLL nor receives supply of a transmission clock from the outside.
The reception apparatus just described cannot correctly sample a signal of a frequency higher than ½ the sampling frequency from the sampling principle. Accordingly, in order to make it possible for the reception apparatus conversely to sample all values correctly, it is necessary to set the frequency of the transmission clock to a value lower than ½ the frequency (sampling frequency) of the reception clock. In other words, if means for establishing synchronism is not prepared in the reception apparatus, the actual transmission capacity drops to a value lower that at least ½ an estimated transmission characteristic, and this deteriorates the efficiency.
FIG. 3 illustrates missing of data which occurs when the frequency of the reception clock is low.
Referring to FIG. 3, the first one of three waveforms from above represents transmission data, and the second waveform represents a reception clock. Further, the third waveform represents reception data successfully obtained by sampling with the reception clock.
In the example illustrated in FIG. 3, although the transmission data are successfully sampled upon sampling at timings from time t1 to time t8, since the frequency of the reception clock is low, the value of 0 which should originally be obtained at time t9 which is the next sampling timing misses.
In this manner, a reception apparatus to which a transmission clock is not supplied from the outside and which does not include a PLL sometimes fails, depending upon the speed of the reception clock, to accurately receive all data transmitted thereto. Further, in order to assure the reliability of the received data, there is the necessity to sufficiently lower the transmission capacity.